View FW802C-DB_1243434.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Data Sheet, Rev. 1 October 2002
TM
FW802C Low-Power PHY IEEE (R) 1394A-2000 Two-Cable Transceiver/Arbiter Device
Distinguishing Features
s s s
Supports connection debounce. Supports multispeed packet concatenation. Supports PHY pinging and remote PHY access packets. Supports full suspend/resume. Supports PHY-link interface initialization and reset. Supports 1394a-2000 register set. Supports LPS/link-on as a part of PHY-link interface. Supports provisions of IEEE 1394-1995 Standard for a High Performance Serial Bus. Fully interoperable with FireWire(R) implementation of IEEE 1394-1995. Reports cable power fail interrupt when voltage at CPS pin falls below 7.5 V. Separate cable bias and driver termination voltage supply for each port. Meets Intel (R) Mobile Power Guideline 2000.
Compliant with IEEE Standard 1394a-2000, IEEE Standard for a High Performance Serial Bus Amendment 1. Low-power consumption during powerdown or microlow-power sleep mode. Supports extended BIAS_HANDSHAKE time for enhanced interoperability with camcorders. While unpowered and connected to the bus, the device will not drive TPBIAS on a connected port even if receiving incoming bias voltage on that port. Does not require external filter capacitors for PLL. Does not require a separate 5 V supply for 5 V link controller interoperability. Interoperable across 1394TM cable with 1394 physical layers (PHY) using 5 V supplies. Interoperable with 1394 link-layer controllers using 5 V supplies.
s
s s s s
s
s
s
s
s s
s
s
s
s
s
s
s
1394a-2000 compliant common-mode noise filter on incoming TPBIAS.
Powerdown features to conserve energy in batterypowered applications include: -- Device powerdown pin. -- Link interface disable using LPS. -- Inactive ports powerdown. -- Automatic microlow-power sleep mode during suspend. Interface to link-layer controller supports Annex J electrical isolation as well as bus-keeper isolation.
Other Features
s s s
s
48-pin TQFP package. Single 3.3 V supply operation. Data interface to link-layer controller provided through 2/4/8 parallel lines at 50 Mbits/s. 25 MHz crystal oscillator and PLL provide transmit/ receive data at 100 Mbits/s, 200 Mbits/s, and 400 Mbits/s, and link-layer controller clock at 50 MHz. Node power-class information signaling for system power management. Multiple separate package signals provided for analog and digital supplies and grounds.
s
s
Features
s
s
Provides two compliant cable ports at 100 Mbits/s, 200 Mbits/s, and 400 Mbits/s. Supports OHCI requirements. Supports arbitrated short bus reset to improve utilization of the bus. Supports ack-accelerated arbitration and fly-by concatenation.
s
s s
s
FW802C Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device
Data Sheet, Rev. 1 October 2002
Table of Contents
Contents Page
Distinguishing Features ............................................................................................................................................1 Features ...................................................................................................................................................................1 Other Features .........................................................................................................................................................1 Description ................................................................................................................................................................3 Signal Information .....................................................................................................................................................6 Application Information ...........................................................................................................................................10 1394 Application Support Contact Information .......................................................................................................11 Crystal Selection Considerations ............................................................................................................................11 Load Capacitance ............................................................................................................................................12 Board Layout ....................................................................................................................................................12 Absolute Maximum Ratings ....................................................................................................................................12 Electrical Characteristics ........................................................................................................................................13 Timing Characteristics ............................................................................................................................................16 Timing Waveforms ..................................................................................................................................................17 Internal Register Configuration ...............................................................................................................................18 Outline Diagrams ....................................................................................................................................................23 48-Pin TQFP ....................................................................................................................................................23 Ordering Information ...............................................................................................................................................23
List of Figures
Figures Page
Figure 1. Block Diagram ........................................................................................................................................ 5 Figure 2. Pin Assignments ..................................................................................................................................... 6 Figure 3. Typical External Component Connections ........................................................................................... 10 Figure 4. Typical Port Termination Network ........................................................................................................ 11 Figure 5. Dn, CTLn, and LREQ Input Setup and Hold Times Waveforms .......................................................... 17 Figure 6. Dn, CTLn Output Delay Relative to SYSCLK Waveforms .................................................................... 17
List of Tables
Tables Page
Table 1. Signal Descriptions................................................................................................................................... 7 Table 2. Absolute Maximum Ratings.................................................................................................................... 12 Table 3. Analog Characteristics............................................................................................................................ 13 Table 4. Driver Characteristics ............................................................................................................................. 14 Table 5. Device Characteristics............................................................................................................................ 15 Table 6. Switching Characteristics ....................................................................................................................... 16 Table 7. Clock Characteristics ............................................................................................................................. 16 Table 8. PHY Register Map for the Cable Environment ...................................................................................... 18 Table 9. PHY Register Fields for the Cable Environment .................................................................................... 18 Table 10. PHY Register Page 0: Port Status Page ............................................................................................. 20 Table 11. PHY Register Port Status Page Fields ................................................................................................ 21 Table 12. PHY Register Page 1: Vendor Identification Page .............................................................................. 22 Table 13. PHY Register Vendor Identification Page Fields ................................................................................. 22
2
Agere Systems Inc.
Data Sheet, Rev. 1 August 2002
FW802C Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device
local system clock, and sent to the associated LLC. The received data is also transmitted (repeated) out of the other active (connected) cable ports. Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during initialization and arbitration. The outputs of these comparators are used by the internal logic to determine the arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this common-mode voltage is used during arbitration to set the speed of the next packet transmission. In addition, the TPB channel monitors the incoming cable common-mode voltage for the presence of the remotely supplied twisted-pair bias voltage. This monitor is called bias-detect. The TPBIAS circuit monitors the value of incoming TPA pair common-mode voltage when local TPBIAS is inactive. Because this circuit has an internal current source and the connected node has a current sink, the monitored value indicates the cable connection status. This monitor is called connect-detect. Both the TPB bias-detect monitor and TPBIAS connect-detect monitor are used in suspend/resume signaling and cable connection detection. The PHY provides a 1.86 V nominal bias voltage for driver load termination. This bias voltage, when seen through a cable by a remote receiver, indicates the presence of an active connection. The value of this bias voltage has been chosen to allow interoperability between transceiver chips operating from 5 V or 3 V nominal supplies. This bias voltage source should be stabilized by using an external filter capacitor of approximately 0.33 F. The transmitter circuitry, the receiver circuitry, and the twisted-pair bias voltage circuity are all disabled with a powerdown condition. The powerdown condition occurs when the PD input is high. The port transmitter circuitry, the receiver circuitry, and the TPBIAS output are also disabled when the port is disabled, suspended, or disconnected. The line drivers in the PHY operate in a highimpedance current mode and are designed to work with external 112 line-termination resistor networks. One network is provided at each end of each twistedpair cable. Each network is composed of a pair of series-connected 56 resistors. The midpoint of the pair of resistors that is directly connected to the twisted-pair A (TPA) signals is connected to the PBIAS voltage signal. The midpoint of the pair of
Description
The Agere Systems Inc. FW802C device provides the analog physical layer functions needed to implement a two-port node in a cable-based IEEE 1394-1995 and IEEE 1394a-2000 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The PHY is designed to interface with a link-layer controller (LLC).
The PHY requires either an external 24.576 MHz crystal or crystal oscillator. The internal oscillator drives an internal phase-locked loop (PLL), which generates the required 400 MHz reference signal. The 400 MHz reference signal is internally divided to provide the 49.152 MHz, 98.304 MHz, and 196.608 MHz clock signals that control transmission of the outbound encoded strobe and data information. The 49.152 MHz clock signal is also supplied to the associated LLC for synchronization of the two chips and is used for resynchronization of the received data. The powerdown function, when enabled by the PD signal high, stops operation of the PLL and disables all circuitry except the cable-not-active signal circuitry. The PHY supports an isolation barrier between itself and its LLC. When /ISO is tied high, the link interface outputs behave normally. When /ISO is tied low, internal differentiating logic is enabled, and the outputs become short pulses, which can be coupled through a capacitor or transformer as described in the IEEE 1394-1995 Annex J. To operate with bus-keeper isolation, the /ISO pin of the FW802C must be tied high. Data bits to be transmitted through the cable ports are received from the LLC on two, four, or eight data lines (D[0:7]), and are latched internally in the PHY in synchronization with the 49.152 MHz system clock. These bits are combined serially, encoded, and transmitted at 98.304 Mbits/s, 196.608 Mbits/s, or 393.216 Mbits/s as the outbound data-strobe information stream. During transmission, the encoded data information is transmitted differentially on the TPA and TPB cable pair(s). During packet reception, the TPA and TPB transmitters of the receiving cable port are disabled, and the receivers for that port are enabled. The encoded data information is received on the TPA and TPB cable pair. The received data-strobe information is decoded to recover the receive clock signal and the serial data bits. The serial data bits are split into two, four, or eight parallel streams, resynchronized to the Agere Systems Inc.
3
FW802C Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device
Data Sheet, Rev. 1 August 2002
in a repeater mode. When the power supply of the PHY is removed while the twisted-pair cables are connected, the PHY transmitter and receiver circuitry has been designed to present a high impedance to the cable in order to not load the TPBIAS signal voltage on the other end of the cable. For reliable operation, the TPBn signals must be terminated using the normal termination network regardless of whether a cable is connected to a port or not connected to a port. For those applications, when FW802C is used with one of the ports not brought out to a connector, those unused ports may be left unconnected without normal termination. When a port does not have a cable connected, internal connectdetect circuitry will keep the port in a disconnected state. Note: All gap counts on all nodes of a 1394 bus must be identical. This may be accomplished by using PHY configuration packets (see Section 4.3.4.3 of IEEE 1394-1995 standard) or by using two bus resets, which resets the gap counts to the maximum level (3Fh). The link power status (LPS) signal works with the C/LKON signal to manage the LLC power usage of the node. The LPS signal indicates that the LLC of the node is powered up or powered down. If LPS is inactive for more than 1.2 s and less than 25 s, PHY/link interface is reset. If LPS is inactive for greater than 25 s, the PHY will disable the PHY/link interface to save power. FW802C continues its repeater function. If the PHY then receives a link-on packet, the C/LKON signal is activated to output a 6.114 MHz signal, which can be used by the LLC to power itself up. Once the LLC is powered up, the LPS signal communicates this to the PHY and the PHY/link interface is enabled. C/LKON signal is turned off when LPS is active or when a bus reset occurs, provided the interrupt that caused C/LKON is not present. When the PHY/link interface is in the disabled state, the FW802C will automatically enter a low-power mode, if all ports are inactive (disconnected, disabled, or suspended). In this low-power mode, the FW802C disables its PLL and also disables parts of reference circuitry depending on the state of the ports (some reference circuitry must remain active in order to detect incoming TP bias). The lowest power consumption (the microlow-power sleep mode) is attained when all ports are either disconnected or disabled with the ports interrupt enable bit cleared. The FW802C will exit the lowpower mode when the LPS input is asserted high or when a port event occurs that requires the FW802C Agere Systems Inc.
Description (continued)
resistors that is directly connected to the twisted-pair B (TPB) signals is coupled to ground through a parallel RC network with recommended resistor and capacitor values of 5 k and 220 pF, respectively. The value of the external resistors are specified to meet the standard specifications when connected in parallel with the internal receiver circuits. The driver output current, along with other internal operating currents, is set by an external resistor. This resistor is connected between the R0 and R1 signals and has a value of 2.49 k 1%. The FW802C supports suspend/resume as defined in the IEEE 1394a-2000 specification. The suspend mechanism allows an FW802C port to be put into a suspended state. In this state, a port is unable to transmit or receive data packets; however, it remains capable of detecting connection status changes and detecting incoming TPBias. When all ports of the FW802C are suspended, all circuits except the bias voltage reference generator and the bias detection circuits are powered down, resulting in significant power savings. The use of suspend/resume is recommended. The signal, C/LKON, as an input, indicates whether a node is a contender for bus manager. When the C/LKON signal is asserted, it means the node is a contender for bus manager. When the signal is not asserted, it means that the node is not a contender. The C bit corresponds to bit 20 in the self-ID packet (see Table 4-29 of the IEEE 1394-1995 standard for additional details). The power class bits of the self-ID packet do not have a default value. These bits can be initialized and read/ written through the LLC using Figure 6-1 (PHY Register Map) of the IEEE 1394a-2000 standard. See Table 8 for the address space of the Pwr_class register. A powerdown signal (PD) is provided to allow a powerdown mode where most of the PHY circuits are powered down to conserve energy in battery-powered applications. The internal logic in FW802C is reset as long as the powerdown signal is asserted. A cable status signal, CNA, provides a high output when none of the twisted-pair cable ports are receiving incoming bias voltage. This output is not debounced. The CNA output can be used to determine when to power the PHY down or up. In the powerdown mode, all circuitry is disabled except the CNA circuitry. It should be noted that when the device is powered down, it does not act
4
Data Sheet, Rev. 1 August 2002
FW802C Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device
Two of the signals are used to set up various test conditions used in manufacturing. These signals (SE and SM) should be connected to VSS for normal operation.
Description (continued)
to become active in order to respond to the event or to notify the LLC of the event (e.g., incoming bias or disconnection is detected on a suspended port, a new connection is detected on a nondisabled port, etc.). The SYSCLK output will become active (and the PHY/ link interface will be initialized and become operative) within 3 ms after LPS is asserted high, when the FW802C is in the low-power mode.
CPS LPS /ISO CNA SYSCLK LREQ CTL0 CTL1 D0 D1 D2 D3 D4 D5 D6 D7 LINK INTERFACE I/O TPA0+ TPA0- ARBITRATION AND CONTROL STATE MACHINE LOGIC RECEIVED DATA DECODER/ RETIMER BIAS VOLTAGE AND CURRENT GENERATOR R0 R1
TPBIAS0
CABLE PORT 0 TPB0+ TPB0-
C/LKON SE SM
PD TPA1+ TPA1- TPBIAS1 TPB1+ TPB1-
/RESET
TRANSMIT DATA ENCODER
CABLE PORT 1
CRYSTAL OSCILLATOR, PLL SYSTEM, AND CLOCK GENERATOR
XI XO
5-5459.f (F)
Figure 1. Block Diagram
Agere Systems Inc.
5
FW802C Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device
Data Sheet, Rev. 1 October 2002
Signal Information
SYSCLK
/RESET
PLLVDD
PLLVSS
LREQ
VDD
VSS
VSS
XO
R1 38
48
47
46
45
44
43
42
41
40
39
37
R0
XI
CTL0 CTL1 D0 D1 VDD D2 D3 D4 D5 D6 D7 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 AGERE FW802C PIN #1 IDENTIFIER
36 35 34 33 32 31 30 29 28 27 26 25
VSSA TPBIAS1 TPA1+ TPA1- TPB1+ TPB1- VDDA TPBIAS0 TPA0+ TPA0- TPB0+ TPB0-
C/LKON
PD
CNA
CPS
LPS
VDD
SE
VDDA
Note: Active-low signals are indicated by "/" at the beginning of signal names, within this document.
5-6236.b (F)
Figure 2. Pin Assignments
6
VSSA
VSS
/ISO
SM
Agere Systems Inc.
Data Sheet, Rev. 1 October 2002
FW802C Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device
Signal Information (continued)
Table 1. Signal Descriptions Pin 17 Signal* C/LKON Type I/O Name/Description Bus Manager Capable Input and Link-On Output. On hardware reset, this pin is used to set the default value of the contender status indicated during self-ID. The bit value programming is done by tying the signal through a 10 k resistor to VDD (high, bus manager capable) or to GND (low, not bus manager capable). Using either the pull-up or pull-down resistor allows the link-on output to override the input value when necessary. After hardware reset, this pin is set as an output. If the LPS is inactive, C/LKON indicates one of the following events by asserting a 6.114 MHz signal. 1. FW802C receives a link-on packet addressed to this node. 2. Port_event register bit is 1. 3. Any of the Timeout, Pwr_Fail, or Loop register bits are 1 and the Resume_int register bit is also 1. Once activated, the C/LKON output will continue active until the LPS becomes active. The PHY also deasserts the C/LKON output when a bus reset occurs, if the C/LKON is active due solely to the reception of a link-on packet. Note: If an interrupt condition exists that would otherwise cause the C/LKON output to be activated if the LPS were inactive, the C/LKON output will be activated when the LPS subsequently becomes inactive. 13 CNA O Cable-Not-Active Output. CNA is asserted high when none of the PHY ports are receiving an incoming bias voltage. This circuit remains active during the powerdown mode. Cable Power Status. CPS is normally connected to the cable power through a 400 k resistor. This circuit drives an internal comparator that detects the presence of cable power. This information is maintained in one internal register and is available to the LLC by way of a register read (see Table 8, Register 0). Control I/O. The CTLn signals are bidirectional communications control signals between the PHY and the LLC. These signals control the passage of information between the two devices. Bus-keeper circuitry is built into these terminals. Data I/O. The Dn signals are bidirectional and pass data between the PHY and the LLC. Bus-keeper circuitry is built into these terminals. Link Interface Isolation Disable Input (Active-Low). /ISO controls the operation of an internal pulse differentiating function used on the PHY-LLC interface signals, CTLn and Dn, when they operate as outputs. When /ISO is asserted low, the isolation barrier is implemented between PHY and its LLC (as described in Annex J of IEEE 1394-1995). /ISO is normally tied high to disable isolation differentiation. Bus-keepers are enabled when /ISO is high (inactive) on CTL, D, and LREQ. When /ISO is low (active), the bus-keepers are disabled. Please refer to Agere's application note AP98-074CMPR for more information on isolation.
20
CPS
I
1 2 3, 4, 6, 7, 8, 9, 10, 11 19
CTL0 CTL1 D[0:7]
I/O
I/O
/ISO
I
* Active-low signals are indicated by "/" at the beginning of signal names, within this document.
Agere Systems Inc.
7
FW802C Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device
Data Sheet, Rev. 1 October 2002
Signal Information (continued)
Table 1. Signal Descriptions (continued) Pin 14 Signal* LPS Type I Name/Description Link Power Status. LPS is connected to either the VDD supplying the LLC or to a pulsed output that is active when the LLC is powered for the purpose of monitoring the LLC power status. If LPS is inactive for more than 1.2 s and less than 25 s, interface is reset. If LPS is inactive for greater than 25 s, the PHY will disable the PHY/Link interface to save power. FW802C continues its repeater function. Link Request. LREQ is an output from the LLC that requests the PHY to perform some service. Bus-keeper circuitry is built into this terminal. Powerdown. When asserted high, PD turns off all internal circuitry except the bias-detect circuits that drive the CNA signal. Internal FW802C logic is kept in the reset state as long as PD is asserted. PD terminal is provided for backward compatibility. It is recommended that the FW802C be allowed to manage its own power consumption using suspend/resume in conjunction with LPS. C/LKON features are defined in 1394a-2000. Power for PLL Circuit. PLLVDD supplies power to the PLL circuitry portion of the device. Ground for PLL Circuit. PLLVSS is tied to a low-impedance ground plane. Current Setting Resistor. An internal reference voltage is applied to a resistor connected between R0 and R1 to set the operating current and the cable driver output current. A low temperature-coefficient resistor (TCR) with a value of 2.49 k 1% should be used to meet the IEEE 1394-1995 standard requirements for output voltage limits. Reset (Active-Low). When /RESET is asserted low (active), the FW802C is reset. An internal pull-up resistor, which is connected to VDD, is provided, so only an external delay capacitor is required. This input is a standard logic buffer and can also be driven by an open-drain logic output buffer. Test Mode Control. SE is used during the manufacturing test and should be tied to VSS. Test Mode Control. SM is used during the manufacturing test and should be tied to VSS. System Clock. SYSCLK provides a 49.152 MHz clock signal, which is synchronized with the data transfers to the LLC.
48 18
LREQ PD
I I
41 42 37 38 45
PLLVDD PLLVSS R0 R1 /RESET
-- -- I
I
21 22 46 28 34 27 33 26 32
SE SM SYSCLK TPA0+ TPA1+ TPA0- TPA1- TPB0+ TPB1+
I I O
Analog I/O Portn, Port Cable Pair A. TPAn is the port A connection to the twistedpair cable. Board traces from each pair of positive and negative differential signal pins should be kept matched and as short as possible to the external load resistors and to the cable connector. Analog I/O Portn, Port Cable Pair A. TPAn is the port A connection to the twistedpair cable. Board traces from each pair of positive and negative differential signal pins should be kept matched and as short as possible to the external load resistors and to the cable connector. Analog I/O Portn, Port Cable Pair B. TPBn is the port B connection to the twistedpair cable. Board traces from each pair of positive and negative differential signal pins should be kept matched and as short as possible to the external load resistors and to the cable connector. Agere Systems Inc.
* Active-low signals are indicated by "/" at the beginning of signal names, within this document.
8
Data Sheet, Rev. 1 October 2002
FW802C Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device
Signal Information (continued)
Table 1. Signal Descriptions (continued) Pin 25 31 29 35 5, 16, 39 23, 30 12, 15, 40, 47 24, 36 43 Signal* TPB0- TPB1- TPBIAS0 TPBIAS1 VDD VDDA VSS VSSA XI Type Name/Description
Analog I/O Portn, Port Cable Pair B. TPBn is the port B connection to the twistedpair cable. Board traces from each pair of positive and negative differential signal pins should be kept matched and as short as possible to the external load resistors and to the cable connector. Analog I/O Portn, Twisted-Pair Bias. TPBIAS provides the 1.86 V nominal bias voltage needed for proper operation of the twisted-pair cable drivers and receivers and for sending a valid cable connection signal to the remote nodes. -- -- -- -- -- Digital Power. VDD supplies power to the digital portion of the device. Analog Circuit Power. VDDA supplies power to the analog portion of the device. Digital Ground. All VSS signals should be tied to the low-impedance ground plane. Analog Circuit Ground. All VSSA signals should be tied together to a lowimpedance ground plane. Crystal Oscillator. XI and XO connect to a 24.576 MHz parallel resonant fundamental mode crystal. Although, when a 24.576 MHz clock source is used, it can be connected to XI with XO left unconnected. The optimum values for the external shunt capacitors are dependent on the specifications of the crystal used. For more details, see Crystal Selection Considerations in the Application Information section.
44
XO
* Active-low signals are indicated by "/" at the beginning of signal names, within this document.
Agere Systems Inc.
9
FW802C Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device
Data Sheet, Rev. 1 October 2002
Application Information
510 k
0.1 F 2.49 k SYSCLK /RESET PLLVDD PLLVSS LREQ
24.576 MHz
VDD
VSS
VSS
XO
R1 38
48
47
46
45
44
43
42
41
40
39
37
R0
XI
CTL0 CTL1 D0 D1 VDD D2 D3 D4 D5 D6 D7 VSS
1 2 3 4 5 6 AGERE FW802C 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PIN #1 IDENTIFIER
36 35 34 33 32 31 30 29 28 27 26 25
VSSA TPBIAS1 TPA1+ TPA1- TPB1+ TPB1- VDDA TPBIAS0 TPA0+ TPA0- TPB0+ TPB0- PORT 0* PORT 1*
C/LKON
/ISO
CNA
CPS
LPS
VDD
SM
PD
SE
VDDA
400 k
CABLE POWER
VSSA
VSS
5-6767 (F)
* See Figure 4 for typical port termination network.
Figure 3. Typical External Component Connections
10
Agere Systems Inc.
Data Sheet, Rev. 1 August 2002
FW802C Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device
Application Information (continued)
35 34 33 32 31 29 28 27 26 25 TPBIAS1 TPA1+ TPA1- TPB1+ TPB1- TPBIAS0 56 TPA0+ TPA0- TPB0+ TPB0- 56 56 3 4 0.33 F 56 TPBIAS1
USE SAME PORT TERMINATION NETWORK AS ILLUSTRATED BELOW.
5
6
IEEE 1394-1995 STANDARD CONNECTOR
220 pF
5 k
1
2
VP CABLE POWER
VG
5-6930 (F)
Figure 4. Typical Port Termination Network
1394 Application Support Contact Information
E-mail: support1394@agere.com
Crystal Selection Considerations
The FW802C is designed to use an external 24.576 MHz crystal connected between the XI and XO terminals to provide the reference for an internal oscillator circuit. IEEE 1394a-2000 standard requires that FW802C have less than 100 ppm total variation from the nominal data rate, which is directly influenced by the crystal. To achieve this, it is recommended that an oscillator with a nominal 50 ppm or less frequency tolerance be used. The total frequency variation must be kept below 100 ppm from nominal with some allowance for error introduced by board and device variations. Trade offs between frequency tolerance and stability may be made as long as the total frequency variation is less than 100 ppm.
Agere Systems Inc.
11
FW802C Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device
Data Sheet, Rev. 1 October 2002
Crystal Selection Considerations (continued)
Load Capacitance
The frequency of oscillation is dependent upon the load capacitance specified for the crystal, in parallel resonant mode crystal circuits. Total load capacitance (CL) is a function of not only the discrete load capacitors, but also capacitances from the FW802C board traces and capacitances of the other FW802C connected components. The values for load capacitors (CA and CB) should be calculated using this formula: CA = CB = (CL - Cstray) x 2 Where: CL = load capacitance specified by the crystal manufacturer Cstray = capacitance of the board and the FW802C, typically 2--3 pF
Board Layout
The layout of the crystal portion of the PHY circuit is important for obtaining the correct frequency and minimizing noise introduced into the FW802C PLL. The crystal and two load capacitors should be considered as a unit during layout. They should be placed as close as possible to one another, while minimizing the loop area created by the combination of the three components. Minimizing the loop area minimizes the effect of the resonant current that flows in this resonant circuit. This layout unit (crystal and load capacitors) should then be placed as close as possible to the PHY XI and XO terminals to minimize trace lengths. Vias should not be used to route the XI and XO signals.
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Table 2. Absolute Maximum Ratings Parameter Supply Voltage Range Input Voltage Range* Output Voltage Range at Any Output Operating Free Air Temperature Storage Temperature Range Symbol VDD VI VO TA Tstg Min 3.0 -0.5 -0.5 0 -65 Max 3.6 VDD + 0.5 VDD + 0.5 70 150 Unit V V V C C
* Except for 5 V tolerant I/O (CTL0, CTL1, D0--D7, and LREQ) where VI max = 5.5 V.
12
Agere Systems Inc.
Data Sheet, Rev. 1 October 2002
FW802C Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device
Electrical Characteristics
Table 3. Analog Characteristics Parameter Supply Voltage Differential Input Voltage Test Conditions Source power node Cable inputs, 100 Mbits/s operation Cable inputs, 200 Mbits/s operation Cable inputs, 400 Mbits/s operation Cable inputs, during arbitration TPB cable inputs, speed signaling off TPB cable inputs, S100 speed signaling on TPB cable inputs, S200 speed signaling on TPB cable inputs, S400 speed signaling on TPB cable inputs, speed signaling off TPB cable inputs, S100 speed signaling on TPB cable inputs, S200 speed signaling on TPB cable inputs, S400 speed signaling on TPA, TPB cable inputs, 100 Mbits/s operation TPA, TPB cable inputs, 200 Mbits/s operation TPA, TPB cable inputs, 400 Mbits/s operation Between TPA and TPB cable inputs, 100 Mbits/s operation Between TPA and TPB cable inputs, 200 Mbits/s operation Between TPA and TPB cable inputs, 400 Mbits/s operation -- Symbol VDD--SP VID--100 VID--200 VID--400 VID--ARB VCM VCM--SP--100 VCM--SP--200 VCM--SP--400 VCM VCM--NSP--100 VCM--NSP--200 VCM--NSP--400 -- -- -- -- -- -- VTH+ Min 3.0 142 132 100 168 1.165 1.165 0.935 0.532 1.165 1.165 0.935 0.532 -- -- -- -- -- -- 89 Typ 3.3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max 3.6 260 260 260 265 2.515 2.515 2.515 2.515 2.015 2.015 2.015 2.015 1.08 0.5 0.315 0.8 0.55 0.5 168 Unit V mV mV mV mV V V V V V V V V ns ns ns ns ns ns mV
Common-mode Voltage Source Power Mode
Common-mode Voltage Nonsource Power Mode*
Receive Input Jitter
Receive Input Skew
Positive Arbitration Comparator Input Threshold Voltage Negative Arbitration Comparator Input Threshold Voltage Speed Signal Input Threshold Voltage Output Current TPBIAS Output Voltage Current Source for Connect Detect Circuit
--
VTH-
-168
--
-89
mV
200 Mbits/s 400 Mbits/s TPBIAS outputs At rated I/O current --
VTH--S200 VTH--S400 IO VO ICD
45 266 -5 1.665 --
-- -- -- -- --
139 445 2.5 2.015 76
mV mV mA V A
* For a node that does not source power (see Section 4.2.2.2 in IEEE 1394-1995 Standard).
Agere Systems Inc.
13
FW802C Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device
Data Sheet, Rev. 1 October 2002
Electrical Characteristics (continued)
Table 4. Driver Characteristics Parameter Differential Output Voltage Off-state Common-mode Voltage Driver Differential Current, TPA+, TPA-, TPB+, TPB- Common-mode Speed Signaling Current, TPB+, TPB- Test Conditions 56 load Drivers disabled Driver enabled, speed signaling off* 200 Mbits/s speed signaling enabled 400 Mbits/s speed signaling enabled Symbol VOD VOFF IDIFF ISP ISP Min 172 -- -1.05 -2.53 -8.1 Typ -- -- -- -- -- Max 265 20 1.05 -4.84 -12.4 Unit mV mV mA mA mA
* Limits are defined as the algebraic sum of TPA+ and TPA- driver currents. Limits also apply to TPB+ and TPB- as the algebraic sum of driver currents. Limits are defined as the absolute limit of each of TPB+ and TPB- driver currents.
14
Agere Systems Inc.
Data Sheet, Rev. 1 October 2002
FW802C Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device
Electrical Characteristics (continued)
Table 5. Device Characteristics Parameter Supply Current: One Port Active All Ports Active Microlow-Power Sleep Mode PD = 1 High-level Output Voltage Low-level Output Voltage High-level Input Voltage Low-level Input Voltage Pull-up Current, /RESET Input Powerup Reset Time, /RESET Input Rising Input Threshold Voltage /RESET Input Output Current Test Conditions VDD = 3.3 V IDD IDD IDD IDD IOH max, VDD = min IOL min, VDD = max CMOS inputs CMOS inputs VI = 0 V VI = 0 V -- SYSCLK Control, data CNA C/LKON Input Current, LREQ, LPS, PD, SE, SM, PC[0:2] Inputs Off-state Output Current, CTL[0:1], D[0:7], C/LKON I/Os Power Status Input Threshold Voltage, CPS Input Rising Input Threshold Voltage*, LREQ, CTLn, Dn Falling Input Threshold Voltage*, LREQ, CTLn, Dn Bus Holding Current, LREQ, CTLn, Dn Rising Input Threshold Voltage LPS Falling Input Threshold Voltage LPS VI = VDD or 0 V VOH VOL VIH VIL II -- VIRST IOL/IOH @ TTL IOL/IOH @ CMOS IOL/IOH IOL/IOH II -- -- -- -- VDD - 0.4 -- 0.7VDD -- 11 2 1.1 -16 -12 -16 -2 -- 54 74 50 50 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.4 -- 0.2VDD 32 -- 1.4 16 12 16 2 1 mA mA A A V V V V A ms V mA mA mA mA A Symbol Min Typ Max Unit
VO = VDD or 0 V 400 k resistor -- -- VI = 1/2(VDD) -- --
IOZ VTH VIT+ VIT- -- VLIH VLIL
-- 7.5 VDD/2 + 0.3 VDD/2 - 0.8 250 -- 0.24VDD + 0.2
-- -- -- -- -- -- --
5 8.5 VDD/2 + 0.8 VDD/2 - 0.3 550 0.24VDD + 1 --
A V V V A V V
* Device is capable of both differentiated and undifferentiated operation.
Agere Systems Inc.
15
FW802C Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device
Data Sheet, Rev. 1 October 2002
Timing Characteristics
Table 6. Switching Characteristics Symbol -- -- tr tf tsu th td Parameter Jitter, Transmit Transmit Skew Rise Time, Transmit (TPA/TPB) Fall Time, Transmit (TPA/TPB) Setup Time, Dn, CTLn, LREQ to SYSCLK Hold Time, Dn, CTLn, LREQ from SYSCLK Delay Time, SYSCLK to Dn, CTLn Measured TPA, TPB Between TPA and TPB 10% to 90% 90% to 10% 50% to 50% 50% to 50% 50% to 50% Test Conditions -- -- RI = 56 , CI = 10 pF RI = 56 , CI = 10 pF See Figure 5. See Figure 5. See Figure 6. Min -- -- -- -- 6 0 1 Typ -- -- -- -- -- -- -- Max 0.15 0.1 1.2 1.2 -- -- 6 Unit ns ns ns ns ns ns ns
Table 7. Clock Characteristics Parameter External Clock Source Frequency Symbol f Min 24.5735 Typ 24.5760 Max 24.5785 Unit MHz
16
Agere Systems Inc.
Data Sheet, Rev. 1 October 2002
FW802C Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device
Timing Waveforms
SYSCLK th tsu Dn, CTLn, LREQ
5-6017.a (F)
Figure 5. Dn, CTLn, and LREQ Input Setup and Hold Times Waveforms
SYSCLK
td
Dn, CTLn
5-6018.a (F)
Figure 6. Dn, CTLn Output Delay Relative to SYSCLK Waveforms
Agere Systems Inc.
17
FW802C Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device
Data Sheet, Rev. 1 October 2002
Internal Register Configuration
The PHY register map is shown below in Table 8. Table 8. PHY Register Map for the Cable Environment Address Bit 0 00002 00012 00102 00112 01002 01012 01102 01112 10002 LCtrl Resume_int RHB IBR Extended (7) Max_speed Contender ISBR Loop Bit 1 Bit 2 Contents Bit 3 Bit 4 Bit 5 Bit 6 R Gap_count Bit 7 PS
Physical_ID
XXXXX XXXXX
Jitter Pwr_fail Timeout
Total_ports Delay Pwr_class Port_event Enab_accel Enab_multi
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX Page_select Port_select XXXXX
Register 0 Page_select
11112
Register 7 Page_select
REQUIRED
XXXXX
RESERVED
The meaning of the register fields within the PHY register map are defined by Table 9 below. Power reset values not specified are resolved by the operation of the PHY state machines subsequent to a power reset. Table 9. PHY Register Fields for the Cable Environment Field Physical_ID Size Type 6 r Power Reset Value 000000 Description The address of this node determined during self-identification. A value of 63 indicates a malconfigured bus; the link will not transmit any packets. When set to one, indicates that this node is the root. Cable power active. Root hold-off bit. When set to one, the force_root variable is TRUE, which instructs the PHY to attempt to become the root during the next tree identify process. Initiate bus reset. When set to one, instructs the PHY to set ibr TRUE and reset_time to RESET_TIME. These values, in turn, cause the PHY to initiate a bus reset without arbitration; the reset signal is asserted for 166 s. This bit is self-clearing. Used to configure the arbitration timer setting in order to optimize gap times according to the topology of the bus. See Section 4.3.6 of IEEE Standard 1394-1995 for the encoding of this field. This field has a constant value of seven, which indicates the extended PHY register map. Agere Systems Inc.
R PS RHB
1 1 1
r r rw
0 -- 0
IBR
1
rw
0
Gap_count
6
rw
3F16
Extended 18
3
r
7
Data Sheet, Rev. 1 October 2002
FW802C Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device
Internal Register Configuration (continued)
Table 9. PHY Register Fields for the Cable Environment (continued) Field Total_ports Max_speed Size Type Power Reset Value 4 3 r r 2 0102 Description The number of ports implemented by this PHY. This count reflects the number. Indicates the speed(s) this PHY supports: 0002 = 98.304 Mbits/s 0012 = 98.304 and 196.608 Mbits/s 0102 = 98.304, 196.608, and 393.216 Mbits/s 0112 = 98.304, 196.608, 393.216, and 786.43 Mbits/s 1002 = 98.304, 196.608, 393.216, 786.432, and 1,572.864 Mbits/s 1012 = 98.304, 196.608, 393.216, 786.432, 1,572.864, and 3,145.728 Mbits/s All other values are reserved for future definition. Worst-case repeater delay, expressed as 144 + (delay * 20) ns. Link Active. Cleared or set by software to control the value of the L bit transmitted in the node's self-ID packet 0, which will be the logical AND of this bit and LPS active. Cleared or set by software to control the value of the C bit transmitted in the self-ID packet. Powerup reset value is set by C/LKON pin. The difference between the fastest and slowest repeater data delay, expressed as (jitter + 1) * 20 ns. Power Class. Controls the value of the pwr field transmitted in the self-ID packet. See Section 4.3.4.1 of IEEE Standard 13941995 for the encoding of this field. Resume Interrupt Enable. When set to one, the PHY will set Port_event to one if resume operations commence for any port. Initiate Short (Arbitrated) Bus Reset. A write of one to this bit instructs the PHY to set ISBR true and reset_time to SHORT_RESET_TIME. These values, in turn, cause the PHY to arbitrate and issue a short bus reset. This bit is self-clearing. Loop Detect. A write of one to this bit clears it to zero. Cable Power Failure Detect. Set to one when the PS bit changes from one to zero. A write of one to this bit clears it to zero. Arbitration State Machine Time-out. A write of one to this bit clears it to zero (see MAX_ARB_STATE_TIME). Port Event Detect. The PHY sets this bit to one if any of connected, bias, disabled, or fault change for a port whose Int_enable bit is one. The PHY also sets this bit to one if resume operations commence for any port and Resume_int is one. A write of one to this bit clears it to zero.
Delay LCtrl
4 1
r rw
0000 1
Contender
1
rw
See description.
Jitter Pwr_class
3 3
r rw
000 See description.
Resume_int ISBR
1 1
rw rw
0 0
Loop Pwr_fail
1 1
rw rw
0 1
Timeout Port_event
1 1
rw rw
0 0
Agere Systems Inc.
19
FW802C Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device
Data Sheet, Rev. 1 October 2002
Internal Register Configuration (continued)
Table 9. PHY Register Fields for the Cable Environment (continued) Field Enab_accel Size Type 1 rw Power Reset Value 0 Description Enable Arbitration Acceleration. When set to one, the PHY will use the enhancements specified in clause 8.11 of 1394a-2000 specification. PHY behavior is unspecified if the value of Enab_accel is changed while a bus request is pending. Enable Multispeed Packet Concatenation. When set to one, the link will signal the speed of all packets to the PHY. Selects which of eight possible PHY register pages are accessible through the window at PHY register addresses 10002 through 11112, inclusive. If the page selected by Page_select presents per-port information, this field selects which port's registers are accessible through the window at PHY register addresses 10002 through 11112, inclusive. Ports are numbered monotonically starting at zero, p0.
Enab_multi Page_select
1 3
rw rw
0 000
Port_select
4
rw
000
The port status page is used to access configuration and status information for each of the PHY's ports. The port is selected by writing zero to Page_select and the desired port number to Port_select in the PHY register at address 01112. The format of the port status page is illustrated by Table 10 below; reserved fields are shown shaded. The meanings of the register fields with the port status page are defined by Table 11. Table 10. PHY Register Page 0: Port Status Page Address Bit 0 10002 10012 10102 10112 11002 11012 11102 11112 AStat Negotiated_speed Bit 1 Bit 2 BStat Int_enable Contents Bit 3 Bit 4 Child Fault Bit 5 Connected Bit 6 Bias Bit 7 Disabled
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX
REQUIRED
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX
RESERVED
20
Agere Systems Inc.
Data Sheet, Rev. 1 October 2002
FW802C Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device
Internal Register Configuration (continued)
The meaning of the register fields with the port status page are defined by Table 11 below. Table 11. PHY Register Port Status Page Fields Field AStat Size Type 2 r Power Reset Value -- Description TPA line state for the port: 002 = invalid 012 = 1 102 = 0 112 = Z TPB line state for the port (same encoding as AStat). If equal to one, the port is a child; otherwise, a parent. The meaning of this bit is undefined from the time a bus reset is detected until the PHY transitions to state T1: Child Handshake during the tree identify process (see Section 4.4.2.2 in IEEE Standard 1394-1995). If equal to one, the port is connected. If equal to one, incoming TPBIAS is detected. If equal to one, the port is disabled. Indicates the maximum speed negotiated between this PHY port and its immediately connected port; the encoding is the same as for the PHY register Max_speed field. Enable port event interrupts. When set to one, the PHY will set Port_event to one if any of connected, bias, disabled, or fault (for this port) change state. Set to one if an error is detected during a suspend or resume operation. A write of one to this bit clears it to zero.
BStat Child
2 1
r r
-- 0
Connected Bias Disabled Negotiated_speed
1 1 1 3
r r rw r
0 0 0 000
Int_enable
1
rw
0
Fault
1
rw
0
Agere Systems Inc.
21
FW802C Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device
Data Sheet, Rev. 1 October 2002
Internal Register Configuration (continued)
The vendor identification page is used to identify the PHY's vendor and compliance level. The page is selected by writing one to Page_select in the PHY register at address 01112. The format of the vendor identification page is shown in Table 12; reserved fields are shown shaded. Table 12. PHY Register Page 1: Vendor Identification Page Address Bit 0 10002 10012 10102 10112 11002 11012 11102 11112 Product_ID Vendor_ID Bit 1 Bit 2 Contents Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Compliance_level
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX
REQUIRED
XXXXX
RESERVED
The meaning of the register fields within the vendor identification page are defined by Table 13. Table 13. PHY Register Vendor Identification Page Fields Field Compliance_level Size Type 8 r Description Standard to which the PHY implementation complies: 0 = not specified 1 = IEEE 1394a-2000 Agere's FW802C compliance level is 1. All other values reserved for future standardization. The company ID or organizationally unique identifier (OUI) of the manufacturer of the PHY. Agere's vendor ID is 00601D16. This number is obtained from the IEEE registration authority committee (RAC). The most significant byte of Vendor_ID appears at PHY register location 10102 and the least significant at 11002. The meaning of this number is determined by the company or organization that has been granted Vendor_ID. Agere's FW802C product ID is 08020116. The most significant byte of Product_ID appears at PHY register location 11012 and the least significant at 11112.
Vendor_ID
24
r
Product_ID
24
r
The vendor-dependent page provides access to information used in manufacturing test of the FW802C.
22
Agere Systems Inc.
Data Sheet, Rev. 1 October 2002
FW802C Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device
Outline Diagrams
48-Pin TQFP
Dimensions are in millimeters .
9.00 0.20 7.00 0.20 1.00 REF PIN #1 IDENTIFIER ZONE
48 37
0.25 GAGE PLANE
1 36
SEATING PLANE 0.45/0.75 7.00 0.20 9.00 0.20
DETAIL A
12
25
13
24
0.106/0.200 DETAIL A DETAIL B 1.40 0.05
0.19/0.27 0.08
M
1.60 MAX SEATING PLANE 0.08 0.50 TYP 0.05/0.15
DETAIL B
5-3080 (F)
Ordering Information
Device Code FW802C-DB Package 48-Pin TQFP Comcode 700032322
Agere Systems Inc.
23
IEEE is a registered trademark and 1394 is a trademark of The Institute of Electrical and Electronics Engineers, Inc. The FireWire logo is a trademark of Apple Computer, Inc. Intel is a registered trademark of Intel Corporation.
For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com N. AMERICA: Agere Systems Inc., Lehigh Valley Central Campus, Room 10A-301C, 1110 American Parkway NE, Allentown, PA 18109-9138 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, FAX (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 755-25881122 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 6778-8833, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44)1344 296 400
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Agere, Agere Systems, and the Agere logo are trademarks of Agere Systems Inc.
Copyright (c) 2002 Agere Systems Inc. All Rights Reserved
October 2002 DS02-362CMPR-1

▲Up To Search▲

Price & Availability of FW802C-DB

	To Download FW802C-DB Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .